Process for fabricating an integrated circuit with a self-aligned contact
US5907781A · kind A · utility
41Cited by
8References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | May 25, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.