Reduced power DRAM device and method
US6356500B1 · kind B1 · utility
114Cited by
3References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Aug 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.