Method for achieving copper fill of high aspect ratio interconnect features
US6436267B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Aug 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.