Dynamic flash memory cells with ultra thin tunnel oxides
US6456535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jun 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angst…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.