Method of manufacturing embedded organic stop layer for dual damascene patterning
US6475810B1 · kind B1 · utility
13Cited by
10References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 10, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Aug 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.