Copper recess process with application to selective capping and electroless plating
US7064064B2 · kind B2 · utility
13Cited by
19References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2005 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Feb 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.