Semiconductor structure having strained semiconductor and method therefor

US7205210B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Alexander L. Barr · Austin, US
• Dejan Jovanovic · Austin, US
• Bich-Yen Nguyen · Austin, US
• Mariam Sadaka · Austin, US
• Voon-Yew Thean · Fishkill, US
• Ted R. White · Austin, US

Key dates

• Filing date: Feb 17, 2004
• Grant date: Apr 17, 2007
• Expiry date: Feb 17, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the <100> direction and at a 45 degree angle to the <100> direction of the base silicon layer of the second silicon.