Template layer formation
US7208357B2 · kind B2 · utility
9Cited by
27References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/933
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.