Structure and method to fabricate high performance MTJ devices for MRAM applications
US7208807B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 15, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Mar 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A high performance MTJ in an MRAM array is disclosed in which the bottom conductor has an amorphous Ta capping layer. A key feature is a surfactant layer comprised of oxygen that is formed on the Ta surface. The resulting smooth and flat Ta capping layer promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-μm2. The MTJ configuraton is extendable to a 0.2×0.4 micron MTJ bit size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.