Structure and method to fabricate high performance MTJ devices for MRAM applications

US7211447B2 · kind B2 · utility

Assignees

• Headway Technologies, Inc. · US
• Applied Spintronics, Inc. · US

Inventors

• Cheng T. Horng · San Jose, US
• Ru-Ying Tong · Los Gatos, US
• Mao-Min Chen · San Jose, US
• Liubo Hong · San Jose, US
• Min Li · Dublin, US

Key dates

• Filing date: Mar 15, 2005
• Grant date: May 1, 2007
• Expiry date: Jun 23, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/01

Abstract

A method of forming a high performance MTJ in an MRAM array is disclosed. A Ta/Ru capping layer in a bottom conductor is sputter etched to remove the Ru layer and form an amorphous Ta capping layer. A key feature is a subsequent surface treatment of the Ta capping layer in a transient vacuum chamber where a self-annealing occurs and a surfactant layer is formed on the Ta surface. The resulting smooth and flat Ta surface promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-μm2.