Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

US7241696B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Infineon Technologies AG · DE

Inventors

• Larry Clevenger · Lagrangeville, US
• Timothy J. Dalton · Ridgefield, US
• Mark Hoinkis · Fishkill, US
• Steffen K. Kaldor · Fishkill, US
• Kaushik A. Kumar · Heverlee, BE
• Douglas C. La Tulipe, Jr. · Albany, US
• Soon-Cheon Seo · White Plains, US
• Andrew H. Simon · Fishkill, US
• Yun-Yu Wang · Poughquag, US
• Chih-Chao Yang · Glenmont, US
• Haining Yang · Wappingers Falls, US

Key dates

• Filing date: Dec 11, 2002
• Grant date: Jul 10, 2007
• Expiry date: May 22, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76835
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.