Method of making a dual strained channel semiconductor device

US7282402B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mariam Sadaka · Austin, US
• Alexander L. Barr · Austin, US
• Dejan Jovanovic · Austin, US
• Bich-Yen Nguyen · Austin, US
• Voon-Yew Thean · Fishkill, US
• Shawn George Thomas · Chesterfield, US
• Ted R. White · Austin, US

Key dates

• Filing date: Mar 30, 2005
• Grant date: Oct 16, 2007
• Expiry date: Jan 18, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.