Gate electrode dopant activation method for semiconductor manufacturing
US7611976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2006 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | May 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer having a dopant concentration within a range from about 1×1019 atoms/cm3 to about 1×1021 atoms/cm3, wherein the doped polycrystalline layer contains silicon or may contain germanium, carbon, or boron. The substrate may be heated to a temperature of about 800° C. or higher, such as about 1,000° C., during the rapid thermal anneal. Subsequently, the doped polycrystalline layer may be exposed to a laser anneal and heated to a temperature of about 1,000° C. or greater, such within a range from about 1,050° C. to about 1,400° C., for about 500 milliseconds or less, such as about 100 milliseconds or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.