Method for forming a semiconductor structure having a strained silicon layer

US7811382B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mariam Sadaka · Austin, US
• Alexander L. Barr · Austin, US
• Bich-Yen Nguyen · Austin, US
• Voon-Yew Thean · Fishkill, US
• Ted R. White · Austin, US

Key dates

• Filing date: May 30, 2006
• Grant date: Oct 12, 2010
• Expiry date: Dec 14, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, …