Dual shallow trench isolation liner for preventing electrical shorts

US8703550B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• STMICROELECTRONICS, INC. · US
• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Bruce B. Doris · Brewster, US
• Shom Ponoth · Irvine, US
• Prasanna Khare · Schenectady, US
• Qing Liu · Guilderland, US
• Nicolas Loubet · Guilderland, US
• Maud Vinet · Voiron, FR

Key dates

• Filing date: Jun 18, 2012
• Grant date: Apr 22, 2014
• Expiry date: Jun 18, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.