Circular transmission line methods compatible with combinatorial processing of semiconductors
US8854067B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Aug 24, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | May 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.