Process for faciltiating fin isolation schemes

US9093496B2 · kind B2 · utility

Assignees

• GlobalFoundries Inc. · KY
• International Business Machines Corporation · US
• STMICROELECTRONICS, INC. · US

Inventors

• Ajey Poovannummoottil Jacob · Watervliet, US
• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US
• Nicolas Loubet · Guilderland, US
• Prasanna Khare · Schenectady, US
• Ramachandra Divakaruni · Ossining, US

Key dates

• Filing date: Jul 18, 2013
• Grant date: Jul 28, 2015
• Expiry date: Aug 31, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0165
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.