Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures
US9099393B2 · kind B2 · utility
2Cited by
4References
14Claims
0Family size
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Key dates
| Filing date | Aug 5, 2013 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Aug 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0193
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.