Fin transformation process and isolation structures facilitating different Fin isolation schemes
US9349730B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 18, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02255
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.