Semiconductor devices with dummy gate structures partially on isolation regions
US9496354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jul 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.