Cutting fins and gates in CMOS devices

US9721848B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Huiming Bu · Millwood, US
• Kangguo Cheng · Schenectady, US
• Andrew M. Greene · Albany, US
• Dechao Guo · Niskayuna, US
• Sivananda K. Kanakasabapathy · Niskayuna, US
• Gauri Karve · Cohoes, US
• Balasubramanian Pranatharthiharan · Watervliet, US
• Stuart A. Sieg · Albany, US
• John R. Sporre · Albany, US
• Gen Tsutsui · Yokohama, JP
• Rajasekhar Venigalla · Hopewell Junction, US
• Huimei Zhou · Albany, US

Key dates

• Filing date: Oct 28, 2016
• Grant date: Aug 1, 2017
• Expiry date: Oct 28, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.