Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells
US9773773B1 · kind B1 · utility
Assignee
Inventors
- Stephen Lam
- Dennis Ciplickas
- Tomasz Brozek
- Jeremy Cheng
- Simone Comensoli
- Indranil De
- Kelvin Doong
- Hans Eisenmann
- Timothy Fiscus
- Jonathan Haigh
- Christopher Hess
- John Kibarian
- Sherry Lee
- Marci Liao
- Sheng-Che Lin
- Hideki Matsuhashi
- Kimon Michaels
- Conor O'Sullivan
- Markus Rauscher
- Vyacheslav Rovner
- Andrzej Strojwas
- Marcin Strojwas
- Carl Taylor
- Rakesh Vallishayee
- Larg Weiland
- Nobuharu Yokoyama
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/988
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of short-circuit failure modes, including at least one chamfer-short-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one GATECNT-short-related failure mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.