Methods to control fin tip placement

US9812324B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Lei Zhuang · White Plains, US
• Lars Liebmann · Poughquag, US
• Stuart A. Sieg · Albany, US
• Fee Li Lie · Albany, US
• Mahender Kumar · Hopewell Junction, US
• Shreesh Narasimha · Beacon, US
• Ahmed Hassan · Clifton Park, US
• Guillaume Bouche · Albany, US
• Xintuo Dai · Rexford, US

Key dates

• Filing date: Jan 13, 2017
• Grant date: Nov 7, 2017
• Expiry date: Jan 13, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.