Methods of forming a gate contact for a transistor above an active region and the resulting device
US9947589B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | May 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor is formed above an active region. The transistor includes a gate structure, a first gate cap layer and a first sidewall spacer positioned adjacent sidewalls of the gate structure. Source/drain contacts are formed adjacent the first sidewall spacer. The first gate cap layer and a portion of the first sidewall spacer are removed to define a gate contact cavity that exposes a portion of the gate structure and an upper portion of the SD contacts. A second spacer and a conductive gate plug are formed in the gate contact cavity. Upper portions of the SD contacts positioned adjacent the second spacer are removed to define a gate cap cavity. A second gate cap layer is formed in the gate cap cavity. An insulating layer is formed above the second gate cap layer. A first conductive structure is formed in the insulating layer conductively coupled to the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.