Method for forming spacers for a transistor gate
US9583339B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0323
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.