Methods of forming a semiconductor device with a gate contact positioned above the active region

US10204994B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ruilong Xie · Niskayuna, US
• Chanro Park · Clifton Park, US
• Andre P. Labonte · Mechanicville, US
• Lars Liebmann · Poughquag, US
• Nigel G. Cave · Austin, US
• Mark V. Raymond · Austin, US
• Guillaume Bouche · Albany, US
• David E. Brown · Pleasant Valley, US

Key dates

• Filing date: Apr 3, 2017
• Grant date: Feb 12, 2019
• Expiry date: Apr 7, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/259
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.