Preventing strained fin relaxation
US10615278B2 · kind B2 · utility
2Cited by
2References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2017 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Oct 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor structure includes a stained fin, a gate upon the strain fin, and a spacer upon a sidewall of the gate and upon an end surface of the strained fin. The end surface of the strained fin is coplanar with a sidewall of the gate. The spacer limits relaxation of the strained fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.