Built-in self test circuit for segmented static random access memory (SRAM) array input/output

US12170120B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Hitesh Chawla · Manesar, IN
• Tanuj KUMAR · Noida, IN
• Bhupender Singh · Fishkill, US
• Harsh Rawat · Faridabad, IN
• Kedar Janardan Dhori · Ghaziabad, IN
• Manuj AYODHYAWASI · Noida, IN
• Nitin Chawla · Noida, IN
• Promod Kumar · Misterbianco, IT

Key dates

• Filing date: Jul 28, 2023
• Grant date: Dec 17, 2024
• Expiry date: Jul 28, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/3602
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.