Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection

US12353341B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Bhupender Singh · Fishkill, US
• Hitesh Chawla · Manesar, IN
• Tanuj KUMAR · Noida, IN
• Harsh Rawat · Faridabad, IN
• Kedar Janardan Dhori · Ghaziabad, IN
• Promod Kumar · Misterbianco, IT
• Manuj AYODHYAWASI · Noida, IN
• Nitin Chawla · Noida, IN

Key dates

• Filing date: Oct 12, 2023
• Grant date: Jul 8, 2025
• Expiry date: Nov 20, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/16
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.