Method for forming a double-gated semiconductor device

US6838322B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Daniel T. Pham · Clifton Park, US
• Alexander L. Barr · Austin, US
• Leo Mathew · Austin, US
• Bich-Yen Nguyen · Austin, US
• Anne Vandooren · Mazy, BE
• Ted R. White · Austin, US

Key dates

• Filing date: May 1, 2003
• Grant date: Jan 4, 2005
• Expiry date: May 1, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/024

Abstract

A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).