Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device

US6960523B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Michael Maldei · Durham, US
• Prakash Dev · Plano, US
• David M. Dobuzinsky · New Windsor, US
• Johnathan E. Faltermeier · San Jose, US
• Thomas Rupp · Stormville, US
• Chienfan Yu · Highland Mills, US
• Rajesh Rengarajan · Fishkill, US
• John Benedict · New Paltz, US
• Munir-ud-Din Naeem · Poughkeepsie, US

Key dates

• Filing date: Apr 3, 2003
• Grant date: Nov 1, 2005
• Expiry date: Apr 3, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.