Low RC product transistors in SOI semiconductor process

US7037795B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Alexander L. Barr · Austin, US
• Olubunmi O. Adetutu · Austin, US
• Bich-Yen Nguyen · Austin, US
• Marius Orlowski · Meylan, FR
• Mariam Sadaka · Austin, US
• Voon-Yew Thean · Fishkill, US
• Ted R. White · Austin, US

Key dates

• Filing date: Oct 15, 2004
• Grant date: May 2, 2006
• Expiry date: Oct 15, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/021

Abstract

A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.