Graded semiconductor layer

US7241647B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mariam Sadaka · Austin, US
• Shawn George Thomas · Chesterfield, US
• Ted R. White · Austin, US
• Chun-Li Liu · Scottsdale, US
• Alexander L. Barr · Austin, US
• Bich-Yen Nguyen · Austin, US
• Voon-Yew Thean · Fishkill, US

Key dates

• Filing date: Aug 17, 2004
• Grant date: Jul 10, 2007
• Expiry date: Aug 17, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/751

Abstract

A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.