Reducing effective dielectric constant in semiconductor devices

US8129286B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Daniel C. Edelstein · White Plains, US
• Matthew E. Colburn · Hopewell Junction, US
• Edward C. Cooney, III · Jericho, US
• Timothy J. Dalton · Ridgefield, US
• John A. Fitzsimmons · Poughkeepsie, US
• Jeffrey P. Gambino · Gresham, US
• Elbert E. Huang · Carmel, US
• Michael Lane · Somers, US
• Vincent J. McGahay · Poughkeepsie, US
• Lee M. Nicholson · Katonah, US
• Satyanarayana V. Nitta · Poughquag, US
• Sampath Purushothaman · Yorktown Heights, US
• Sujatha Sankaran · New Paltz, US
• Thomas M. Shaw · Peekskill, US
• Andrew H. Simon · Fishkill, US
• Anthony K. Stamper · Williston, US

Key dates

• Filing date: Jun 16, 2008
• Grant date: Mar 6, 2012
• Expiry date: Jun 25, 2030

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/947
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.