Defective P-N junction for backgated fully depleted silicon on insulator MOSFET

US8969966B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• STMICROELECTRONICS, INC. · US
• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US
• Laurent Grenouillet · Voiron, FR
• Ali Khakifirooz · Los Altos, US
• Yannick Le Tiec · Crolles, FR
• Qing Liu · Guilderland, US
• Maud Vinet · Voiron, FR

Key dates

• Filing date: Apr 19, 2013
• Grant date: Mar 3, 2015
• Expiry date: Apr 19, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6708
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.