Dual channel hybrid semiconductor-on-insulator semiconductor devices

US9059041B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• STMICROELECTRONICS, INC. · US
• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US
• Ali Khakifirooz · Los Altos, US
• Qing Liu · Guilderland, US
• Laurent Grenouillet · Voiron, FR
• Yannick Le Tiec · Crolles, FR
• Maud Vinet · Voiron, FR

Key dates

• Filing date: Jul 2, 2013
• Grant date: Jun 16, 2015
• Expiry date: Jul 15, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.