Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

US9219078B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• STMICROELECTRONICS, INC. · US
• GlobalFoundries Inc. · KY

Inventors

• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US
• Ali Khakifirooz · Los Altos, US
• Qing Liu · Guilderland, US
• Nicolas Loubet · Guilderland, US
• Scott Luning · San Francisco, US

Key dates

• Filing date: Apr 18, 2013
• Grant date: Dec 22, 2015
• Expiry date: Apr 18, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.