Low leakage dual STI integrated circuit including FDSOI transistors

US9601511B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• International Business Machines Corporation · US
• STMICROELECTRONICS, INC. · US

Inventors

• Maud Vinet · Voiron, FR
• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US
• Laurent Grenouillet · Voiron, FR
• Ali Khakifirooz · Los Altos, US
• Yannick Le Tiec · Crolles, FR
• Qing Liu · Guilderland, US

Key dates

• Filing date: Feb 28, 2013
• Grant date: Mar 21, 2017
• Expiry date: Feb 28, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.