Preventing strained fin relaxation

US9881937B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US
• Hong He · Schenectady, US
• Sivananda K. Kanakasabapathy · Niskayuna, US
• Gauri Karve · Cohoes, US
• Juntao Li · Cohoes, US
• Fee Li Lie · Albany, US
• Derrick Liu · Albany, US
• Chun Wing Yeung · Niskayuna, US

Key dates

• Filing date: Jan 3, 2017
• Grant date: Jan 30, 2018
• Expiry date: Jan 3, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.