Inventor · Welches, OR, US

George E. Bailey

14Patents
4h-index
9Co-inventors
45Inventor score

Filing activity: May 4, 1998 → Jun 22, 2006

Most-cited inventions

PatentTitleAreaCited byStatus
US6782525B2 Wafer process critical dimension, alignment, and registration analysis simulation tool Physics 14 Expired
US6934929B2 Method for improving OPC modeling Physics 10 Expired
US6102143A Shaped polycrystalline cutter elements Fixed Constructions 7 Expired
US6894762B1 Dual source lithography for direct write application Electricity 6 Expired
US6885436B1 Optical error minimization in a semiconductor manufacturing apparatus Physics 4 Expired
US7005217B2 Chromeless phase shift mask Physics 3 Expired
US6627466B1 Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer Electricity 3 Expired
US7381502B2 Apparatus and method to improve the resolution of photolithography systems by improving the temperature stability of the reticle Physics 2 Active
US7023530B1 Dual source lithography for direct write application Electricity 2 Expired
US7298458B2 Optical error minimization in a semiconductor manufacturing apparatus Physics 1 Active
US7098996B1 Optical error minimization in a semiconductor manufacturing apparatus Physics 1 Expired
US6764749B2 Method to improve the resolution of a photolithography system by use of a coupling layer between the photo resist and the ARC Emerging Cross-Sectional Technologies 0 Expired
US6943055B2 Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer Electricity 0 Expired
US6866970B2 Apparatus and method to improve the resolution of photolithography systems by improving the temperature stability of the reticle Physics 0 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.