Systems and methods for cache optimization

US12056059B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Altug Koker · Cameron Park, US
• Joydeep Ray · Folsom, US
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Abhishek R. Appu · Cameron Park, US
• Aravindh Anantaraman · Folsom, US
• Valentin Andrei · San Jose, US
• Durgaprasad Bilagi · Folsom, US
• Varghese George · Folsom, US
• Brent Insko · Portland, US
• Sanjeev Jahagirdar · Folsom, US
• Scott Janus · Rocklin, US
• Pattabhiraman K · Bengaluru, IN
• SungYe Kim · Folsom, US
• Subramaniam Maiyuran · Citrus, US
• Vasanth Ranganathan · Cameron Park, US
• Lakshminarayanan Striramassarma · Folsom, US
• Xinmin Tian · Union City, US

Key dates

• Filing date: Feb 1, 2022
• Grant date: Aug 6, 2024
• Expiry date: Apr 23, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/302
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods for cache utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.