Multi-tile memory management

US12099461B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek R. Appu · Cameron Park, US
• Altug Koker · Cameron Park, US
• Aravindh Anantaraman · Folsom, US
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Valentin Andrei · San Jose, US
• Nicolas C. Galoppo Von Borries · Portland, US
• Varghese George · Folsom, US
• Mike B. Macpherson · Portland, US
• Subramaniam Maiyuran · Citrus, US
• Joydeep Ray · Folsom, US
• Lakshminarayanan Striramassarma · Folsom, US
• Scott Janus · Rocklin, US
• Brent Insko · Portland, US
• Vasanth Ranganathan · Cameron Park, US
• Kamal Sinha · Rancho Cordova, US
• Arthur Hunter · Cameron Park, US
• Prasoonkumar Surti · Folsom, US
• David Puffer · Tempe, US
• James Valerio · Hillsboro, US
• Ankur N. Shah · Folsom, US

Key dates

• Filing date: Mar 14, 2020
• Grant date: Sep 24, 2024
• Expiry date: Sep 10, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.