Patent · US Active

Systems and methods for cache optimization

US12182035B2 · kind B2 · utility

0Cited by

99References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Altug Koker · Cameron Park, US
Joydeep Ray · Folsom, US
Elmoustapha Ould-Ahmed-Vall · Chandler, US
Abhishek R. Appu · Cameron Park, US
Aravindh Anantaraman · Folsom, US
Valentin Andrei · San Jose, US
Durgaprasad Bilagi · Folsom, US
Varghese George · Folsom, US
Brent Insko · Portland, US
Sanjeev Jahagirdar · Folsom, US
Scott Janus · Rocklin, US
Pattabhiraman K · Bengaluru, IN
SungYe Kim · Folsom, US
Subramaniam Maiyuran · Citrus, US
Vasanth Ranganathan · Cameron Park, US
Lakshminarayanan Striramassarma · Folsom, US
Xinmin Tian · Union City, US

Key dates

Filing date	Mar 14, 2020
Grant date	Dec 31, 2024
Priority date	—
Expiry date	Aug 16, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/302
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.