Reliability barrier integration for Cu application

US7026238B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Ming Xi · Palo Alto, US
• Paul Smith · San Jose, US
• Ling Chen · Sunnyvale, US
• Michael Yang · Fremont, US
• Mei Chang · San Jose, US
• Fusen Chen · Dallas, US
• Christophe Marcadal · Sunnyvale, US
• Jenny Lin · Saratoga, US

Key dates

• Filing date: Jan 17, 2002
• Grant date: Apr 11, 2006
• Expiry date: Mar 11, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.