Forming interconnects with air gaps

US7790601B1 · kind B1 · utility

Assignees

• International Business Machines Corporation · US
• Freeescale Semiconductor, Inc. · US

Inventors

• Samuel S. Choi · Hopewell Junction, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Maxime Darnon · White Plains, US
• Daniel C. Edelstein · White Plains, US
• Satyanarayana V. Nitta · Poughquag, US
• Shom Ponoth · Irvine, US
• Pak Leung · Cedar Park, US

Key dates

• Filing date: Sep 17, 2009
• Grant date: Sep 7, 2010
• Expiry date: Sep 17, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31111
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.