Defective P-N junction for backgated fully depleted silicon on insulator mosfet
US9373507B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Feb 10, 2015 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Feb 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6708
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.