Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same
US6127255A · kind A · utility
Assignees
Inventors
- Jun Sugiura
- Osamu Tsuchiya
- Makoto Ogasawara
- Fumio Ootsuka
- Kazuyoshi Torii
- Isamu Asano
- Nobuo Owada
- Mitsuaki Horiuchi
- Tsuyoshi Tamaru
- Hideo Aoki
- Nobuhiro Otsuka
- Seiichirou Shirai
- Masakazu Sagawa
- Yoshihiro Ikeda
- Masatoshi Tsuneoka
- Toru Kaga
- Tomotsugu Shimmyo
- Hidetsugu Ogishi
- Osamu Kasahara
- Hiromichi Enami
- Atsushi Wakahara
- Hiroyuki Akimori
- Sinichi Suzuki
- Keisuke Funatsu
- Yoshinao Kawasaki
- Tunehiko Tubone
- Takayoshi Kogano
- Ken Tsugane
Key dates
| Filing date | Oct 3, 1997 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Oct 3, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.