Inventor · Phoenix, AZ, US

Jay A. Yoder

24Patents
5h-index
15Co-inventors
66Inventor score

Filing activity: Oct 15, 2002 → Jun 6, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8664089B1 Semiconductor die singulation method Electricity 16 Active
US6768186B2 Semiconductor device and laminated leadframe package Electricity 11 Expired
US7298034B2 Multi-chip semiconductor connector assemblies Electricity 10 Expired
US8319323B2 Electronic package having down-set leads and method Emerging Cross-Sectional Technologies 8 Active
US9484210B2 Semiconductor die singulation method Electricity 6 Active
US7202105B2 Multi-chip semiconductor connector assembly method Electricity 5 Expired
US9034733B2 Semiconductor die singulation method Electricity 4 Active
US9847219B2 Semiconductor die singulation method Electricity 2 Active
US7202106B2 Multi-chip semiconductor connector and method Electricity 2 Expired
US7588999B2 Method of forming a leaded molded array package Electricity 2 Active
US8574961B2 Method of marking a low profile packaged semiconductor device Electricity 1 Active
US7875964B2 Multi-chip semiconductor connector and method Electricity 1 Active
US7508060B2 Multi-chip semiconductor connector assemblies Electricity 1 Active
US9870986B2 Single or multi chip module package and related methods Electricity 0 Active
US9911684B1 Holes and dimples to control solder flow Electricity 0 Active
US7498195B2 Multi-chip semiconductor connector assembly method Electricity 0 Active
US11710686B2 Semiconductor package structures and methods of manufacture Electricity 0 Active
US10522448B2 Single or multi chip module package and related methods Electricity 0 Active
US7598123B2 Semiconductor component and method of manufacture Electricity 0 Active
US11984388B2 Semiconductor package structures and methods of manufacture Electricity 0 Active
US9558968B2 Single or multi chip module package and related methods Electricity 0 Active
US7820528B2 Method of forming a leaded molded array package Electricity 0 Active
US8253239B2 Multi-chip semiconductor connector Electricity 0 Active
US11217515B2 Semiconductor package structures and methods of manufacture Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.