Michael J. Seddon
169Patents
10h-index
54Co-inventors
83Inventor score
Filing activity: Jun 1, 1998 → Jun 13, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6300679A | Flexible substrate for packaging a semiconductor component | Electricity | 163 | Expired |
| US6164523A | Electronic component and method of manufacture | Emerging Cross-Sectional Technologies | 124 | Expired |
| US7989319B2 | Semiconductor die singulation method | Electricity | 53 | Active |
| US8012857B2 | Semiconductor die singulation method | Electricity | 53 | Active |
| USD489338S1 | Packaged semiconductor device | General | 40 | Expired |
| USD510728S1 | Semiconductor device package | General | 34 | Expired |
| USD504874S1 | Semiconductor device package | General | 32 | Expired |
| US8384231B2 | Method of forming a semiconductor die | Electricity | 31 | Active |
| US7319266B2 | Encapsulated electronic device structure | Electricity | 22 | Expired |
| US8664089B1 | Semiconductor die singulation method | Electricity | 16 | Active |
| US9337098B1 | Semiconductor die back layer separation method | Electricity | 10 | Active |
| US9564409B2 | Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel | Electricity | 10 | Active |
| US8292690B2 | Thinned semiconductor wafer and method of thinning a semiconductor wafer | Electricity | 10 | Active |
| US9793186B1 | Semiconductor wafer and method of backside probe testing through opening in film frame | Electricity | 9 | Active |
| US10388526B1 | Semiconductor wafer thinning systems and related methods | Electricity | 8 | Active |
| US9847310B2 | Flip chip bonding alloys | Emerging Cross-Sectional Technologies | 7 | Active |
| US10607889B1 | Jet ablation die singulation systems and related methods | Electricity | 6 | Active |
| US8084335B2 | Method of thinning a semiconductor wafer using a film frame | Electricity | 6 | Active |
| US9484210B2 | Semiconductor die singulation method | Electricity | 6 | Active |
| US10090233B2 | Semiconductor device and method of forming micro interconnect structures | Electricity | 5 | Active |
| US7755179B2 | Semiconductor package structure having enhanced thermal dissipation characteristics | Electricity | 5 | Expired |
| US9852972B2 | Semiconductor device and method of aligning semiconductor wafers for bonding | Electricity | 4 | Active |
| US7265454B2 | Semiconductor device and method of producing high contrast identification mark | Electricity | 4 | Active |
| US10573803B1 | Current sensor packages with through hole in semiconductor | Physics | 4 | Active |
| US7135356B2 | Semiconductor device and method of producing a high contrast identification mark | Electricity | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.