Balancing NFET and PFET performance using straining layers

US8106462B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Freeescale Semiconductor, Inc. · US
• Infineon Technologies North America Corp. · US
• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Xiangdong Chen · Irvine, US
• Weipeng Li · Beacon, US
• Anda C. Mocuta · Hopewell Junction, US
• Dae-Gyu Park · Seojong-myeon, KR
• Melanie J. Sherony · Fishkill, US
• Kenneth J. Stein · Sandy Hook, US
• Haizhou Yin · Poughkeepsie, US
• Franck Arnaud · Meylan, FR
• Jin-Ping Han · Fishkill, US
• Laegu Kang · Hopewell Junction, US
• Yong Meng Lee · Singapore, SG
• Young Way Teh · Singapore, SG
• Voon-Yew Thean · Fishkill, US
• Da Zhang · Hopewell Junction, US

Key dates

• Filing date: Jan 14, 2010
• Grant date: Jan 31, 2012
• Expiry date: Jul 26, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.